$past in SV Assertions

[Bhaskar44]

Hi

I was trying to develop an SVA using $past.

Prob stmt: When I see a rising, check that busy was asserted sometime before(any number of clock cycles earlier).

assert property(@(negedge clk)($rose(a)|->$past(busy,[1:$]));

However I get syntax error, doesn’t past support [1:] ?

Or is there a better way I can achieve the functionality check ?

Any help is much appreciated.

Regards

[ben2]

In reply to bharath_1800:

assert property(@(negedge clk)($rose(a)|->$past(busy,[1:$])); 

Questions for you:

1. How often is busy set to 1’b1?
2. When is busy reset?

An easy solution is to set a latch (ambusy) when busy is set. Reset the latch (ambusy) when the assertion passes or fails. For example:

import uvm_pkg::*; `include "uvm_macros.svh" 
module top; 
    timeunit 1ns;     timeprecision 100ps;    
    bit clk,busy, a; 
    bit ambusy; // ff
    always @(posedge clk)  if(busy) ambusy <= 1'b1;
    ap_a_was_bysy: assert property(@(negedge clk)$rose(a)|-> ambusy) 
                            ambusy=1'b0; else ambusy=1'b0;
    initial forever #10 clk=!clk;  
    
    initial begin 
        repeat(2000) begin 
            @(posedge clk);   
            if (!randomize(a, busy)  with 
            { a dist {1'b1:=1, 1'b0:=3}; 
              busy dist {1'b1:=1, 1'b0:=6}; 
        }) `uvm_error("MYERR", "This is a randomize error")
    end 
    $stop; 
end 
endmodule   
  

Ben Cohen
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