Passing Unpacked Array of Packed Array as task arguments

SystemVerilog
, ,
1

task xyz(output op, output bit [width-1:0] write_data );

I have my task xyz definiton in an interface. I want to call this task from my testbench.sv

So, how should I call it? I am trying to call it in this manner but getting an error:
xyz(1’b0, bit[width-1:0] write_data )

What’s the correct way of passing an unpacked array of packed array as task arguments?

2

In reply to AkhilMehta:

I am not sure what kind of error you are getting.
But, by looking into way of calling task xyz is not proper.
Because op is declare as output. So, you can not use 1’b0.( Facing Illegal task argument error )
Below code work for me.


class k;
  parameter width = 1;
  
  bit [width:0] data_t[];
  bit op_t;
  
  task xyz(output op, output bit [width:0] write_data []);
    write_data = '{1,2,3,4,5};
    op = 1;
  endtask : xyz

  task t;
    xyz(op_t,data_t);
    $display("%d <> %p",op_t,data_t);
  endtask : t
  
endclass : k

module m;
  k k1 = new;
  
  initial begin
    k1.t;
  end
endmodule : m
#
# vsim -voptargs=+acc=npr
# run -all
# 1 <> '{1, 2, 3, 0, 1

Thanks!