Passing RTL hierarchical paths to SV Macros

SystemVerilog
,
1

Hi,
I am writing assertions to do similar checks on around 50 of RTL signals.

  1. What is the best way to do this with minimum lines of code ?
  2. One way I tried to do this was by using macros :
    eg:
    define sram3_clkenable_reg TB.u_top.u_core.u_dig_top.u_pnr.u_hp_dig_top.u_hp_reg.sram3_clk_enable define sram2_clkenable_reg TB.u_top.u_core.u_dig_top.u_pnr.u_hp_dig_top.u_hp_reg.sram2_clk_enable
    define BLOCK_sram3 TB.u_top.u_core.u_dig_top.u_pnr.u_perif.u_top.u_sram_4k_ctrl.clk define BLOCK_sram2 TB.u_top.u_core.u_dig_top.u_pnr.u_perif.u_top.u_sram_4k_2_ctrl.clk
    define sram3_clkenable ..some rtl hierarchy similar to the ones above.. define sram2_clkenable …some rtl hierarchy similar to the ones above…

`define CLOCK_GATE_CHECK(ap_PROP1,ap_PROP2,PROP1,PROP2,CLK_EN,CLK_EN_reg,CLOCK_MOD,clkperiod)
property PROP1;
@(posedge SAMPLECLK) (CLK_EN==0)|->(CLOCK_MOD==0);
endproperty : PROP1
ap_PROP1: assert property (PROP1);
property PROP2;
@(posedge SAMPLECLK) $fell(CLK_EN)|->(CLOCK_MOD==0);
endproperty : PROP2
ap_PROP2 : assert property (PROP2);

CLOCK_GATE_CHECK(ap_SRAM3_CLOCKGATE_CHECK,ap_SRAM3_CLOCKGATERISE_CHECK,SRAM3_CLOCKGATE_CHECK,SRAM3_CLOCKGATERISE_CHECK,sram3_clkenable,sram3_clkenable_reg,BLOCK_sram3,10ns);
CLOCK_GATE_CHECK(ap_SRAM2_CLOCKGATE_CHECK,ap_SRAM2_CLOCKGATERISE_CHECK,SRAM2_CLOCKGATE_CHECK,SRAM2_CLOCKGATERISE_CHECK,sram2_clkenable,sram2_clkenable_reg,BLOCK_sram2,10ns);

I see that the properties aren’t getting triggered. It will be great if some one could provide inputs.

Thanks

2

In reply to SreeramP:

Your code looks incomplete to me. I would recommend to write a checker/propety with arguments and handle this:

consider:


checker vw_clk_gate_chkr (input CLK_EN,CLK_EN_reg,CLOCK_MOD,clkperiod);

  property PROP1;
    @(posedge SAMPLECLK) (CLK_EN==0)|->(CLOCK_MOD==0);
  endproperty : PROP1
  ap_PROP1: assert property (PROP1);

  property PROP2;
    @(posedge SAMPLECLK) $fell(CLK_EN)|->(CLOCK_MOD==0);
  endproperty : PROP2
  ap_PROP2 : assert property (PROP2);

endchecker vw_clk_gate_chkr;

Then instantiate that checker 50 times

Good Luck
Srini

3

In reply to Srini @ CVCblr.com:

Thanks a lot Srini.