Passing parameters to a bind entity

SystemVerilog
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1

Hi all,

I am trying to bind parameters of my rtl to my assertion module.
Parameter values change at the simulation time based on the different configurations and I want them to be bound to the assertions.
Any inputs on whats the best way to do this?

bind rtl_module asst_module asst_module_inst #(
.parameter1 (parameter1),
.parameter2 (parameter2)
)

I tried this way but seems to be not working.

Thanks,
Leela

2

In reply to leela:
It would help greatly if you can explain further what you mean by “not working”. Are you getting a compiler error? Or not getting the results you expect?

You cannot change
parameter values during a simulation; they are pre-simulation constants. You can pass values that change as regular ports to a bound module.

3

In reply to dave_59:

sorry if I was not really clear… I was getting a compiler error… but I think I fixed it and its working now.
I tried binding the parameters as follows:
bind rtl_module asst_module #(
.parameter1 (parameter1),
.parameter2 (parameter2)
)
asst_module_inst (.clk(clk),
.rst(rst));

what i mean by changing the parameters during simulation time is that there are different configurations with different parameter values and it changes based on what configuration i choose.

Thanks Dave!