Passing hierarchy using `define

SystemVerilog
, ,
1

hi,
I’m trying to write an assertion for a module that instantiates a sub-model using a generate block.
I want to use a macro to define the path, i have tried the following:

`define PATH(i) top.sub_model_inst[(i)].sub_model_inst.signal

then using inside a property:

property prop(index);
some_condition |-> `path(index)==0;
endproperty

and finally:


generate
for (genvar i=0;i<PARAM;i++)
begin
    assert property (disable iff(reset) prop(i));
end
endgenerate

what seems to happen is that the PATH macro stays with the first iteration (so PATH will point to sub_model_inst[0] also for the other iterations).

am I doing this wrong? if so what is the right way to do this?

thanks

2

In reply to gidon:

Do provide the error you see. The code below works for me.

`define PATH(i) genblock*.bb.signal

module top;

   bit clk;
   
   initial repeat(10) #5 clk++;
   initial #23 genblock[2].bb.signal = 1;
   
   for(genvar ii=0;ii<3;ii++) begin :genblock
      b bb();
   end
  
   property p(index);
      @(posedge clk) `PATH(index) ==0;
   endproperty

   for(genvar ii=0;ii<3;ii++) 
	assert property ( p(ii) );
endmodule
module b;
   bit signal;
endmodule

Your problem might be related to the fact that macros and compiler directives expand before [I]before* the compiler recognizes any SystemVerilog syntax. Attempts to redefine PATH will have no effect.

3

In reply to dave_59:

thanks Dave.
I’m running the assertions with a formal tool, the first iteration passes (in your example: p(0)) , all other iterations keep the `PATH(0), but change the index in the antecedent (and so assertions fail).

my environment is very similar to your example, except I have a seperate SVA file bind to the ‘top’.
do think that may cause the problem?

4

In reply to gidon:

Hard to say without seeing more code. I would contact your vendor for support where you can share more code. It also might be a tool issue. It would try the same code in simulation.