Pass Sequence as Formal Argument to Checker

SystemVerilog
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1

Hi Everyone,

I found answers of my many question from this forum, and until know I did not ask. Now, I have an confusing question, at least for me.

I am trying to pass seequence as a formal argument to a checker. I got this warnings, I used edaplayground, Mentor for simulation:

*** Error: testbench.sv(93): Use of unclocked sequence as an event is illegal.
** Error: testbench.sv(18): Illegal event value in SVA expression.
** Error (suppressible): testbench.sv(23): (vlog-1957) The sva directive is not sensitive to a clock. Unclocked directives are not supported.*

[i]

As I understand, it says I cannot find clock for sequence and it destroys my property block and assertion call. My code is here : SVA36 - Concurrent Assertions - 34 - Checker_3_X - EDA Playground


//==================================================================
// Checker Block
//==================================================================
//clock için başta event tanımı kullanıldı, bir tip. Olmasa da doğru çalışyıor. 
//reset için ise event çalışmıyor, untyped ya da logic yazılmalı. 
//checker içinde formal argument olarak sequence alınacak. 
checker checker_1 (clock_delay,a,b,sequence sequence_1,event clk = $inferred_clock, /*untyped*/ logic reset = $inferred_disable);

//=================================================
//  Declare property for each of sequence
//  We may use more then one seuqnce in a property
//=================================================
  
  property req_gnt_3to5clock_prop;
  @ (posedge clk)
  disable iff (reset)
     //req[1] |-> req_gnt_3to5clock_seq;
  	 a |-> sequence_1;
endproperty
//=================================================
// Assertion Directive Layer
//=================================================
req_gnt_3to5clock_assert : assert property  (req_gnt_3to5clock_prop)
  $display("** Time : [%0t] - req_gnt_3to5clock_prop PASSED --------", $stime);

endchecker  
//==================================================================
// Checker Block
//==================================================================
  

//+++++++++++++++++++++++++++++++++++++++++++++++++
//   DUT With assertions
//+++++++++++++++++++++++++++++++++++++++++++++++++
module hash_sequence();
  
logic clk = 0;
always #1 clk ++;
  
logic [2:0] req,gnt;
logic reset=0;  

//default clocking ve disable iff yapılıyor, checker bunlardan clock ve reset'i çekiyor.   
default clocking @ (posedge clk); endclocking
default disable iff reset;  

//=================================================
// Shows range usage of $ delay operator
//=================================================
sequence req_gnt_3to5clock_seq;
  req[1] ##[3:$] gnt[1];
  //a ##[clock_delay:$] b;
endsequence  
  
//=================================================
// Drive the input vectors to test assetion
//=================================================
initial begin
  // Init all the values
  reset  <= 0;
  for (int i = 0; i < 3; i++) begin
    req[i] <= 0;
    gnt[i] <= 0;
  end
  @ (posedge clk);
  req[0] <= 1;
  @ (posedge clk);
  gnt[0] <= 1;
  req[0] <= 0;
  @ (posedge clk);
  gnt[0] <= 0;
  req[1] <= 1;
  @ (posedge clk);
  req[1] <= 0;
  repeat(3) @ (posedge clk);
  gnt[1] <= 1;
  @ (posedge clk);
  gnt[1] <= 0;
  req[2] <= 1;
  gnt[2] <= 1;
  @ (posedge clk);
  req[2] <= 0;
  gnt[2] <= 0;
  // Cause assertion to fail
  @ (posedge clk);
  req[0] <= 1;
  repeat(2) @ (posedge clk);
  gnt[0] <= 1;
  req[0] <= 0;
  #30 $finish;
end
  //initialize checker check_1
  checker_1  c1 (3, req[1] ,gnt[1],req_gnt_3to5clock_seq);
	
  initial begin
    $dumpfile("dump.vcd"); 
    $dumpvars;    
  end
endmodule

Thanks…

2

In reply to hcglu:

I am not sure how well supported are the $inferred_clock, $inferred_disable because they are used that often.
Check with your vendor.

3

In reply to ben@SystemVerilog.us:

Thank you ben for your answer but I tried it and it works well.

Firstly, I use edaplaygorund and Mentor Questa 2020.1, it works fine.

Secondly, I tried seperately whether inferring clock and reset work or not, it works, I share the code: SVA35 - Concurrent Assertions - 33 - Checker_2 - EDA Playground

You will see it infers clock and reset from the block where it belongs to.



//==================================================================
// Checker Block
//==================================================================
//clock için başta event tanımı kullanıldı, bir tip. Olmasa da doğru çalışyıor. 
//reset için ise event çalışmıyor, untyped ya da logic yazılmalı. 

//checker checker_1 (clock_delay,a,b, event clk = $inferred_clock, /*reg veya logic*/ untyped reset = $inferred_disable);

//input logic şeklinde daha açık girişler verilebilir. 
checker checker_1 (input logic clock_delay, input logic a, input logic b, event clk = $inferred_clock, /*reg veya logic*/ untyped reset = $inferred_disable);
//=================================================
// Shows range usage of $ delay operator
//=================================================
sequence req_gnt_3to5clock_seq;
  //req[1] ##[3:$] gnt[1];
  a ##[clock_delay:$] b;
endsequence
//=================================================
//  Declare property for each of sequence
//  We may use more then one seuqnce in a property
//=================================================
property req_gnt_3to5clock_prop;
  @ (posedge clk)
  disable iff (reset)
     //req[1] |-> req_gnt_3to5clock_seq;
  	 a |-> req_gnt_3to5clock_seq;
endproperty
//=================================================
// Assertion Directive Layer
//=================================================
req_gnt_3to5clock_assert : assert property  (req_gnt_3to5clock_prop)
  $display("** Time : [%0t] - req_gnt_3to5clock_prop PASSED --------", $stime);

endchecker  
//==================================================================
// Checker Block
//==================================================================
  

//+++++++++++++++++++++++++++++++++++++++++++++++++
//   DUT With assertions
//+++++++++++++++++++++++++++++++++++++++++++++++++
module hash_sequence();
  
logic clk = 0;
always #1 clk ++;
  
logic [2:0] req,gnt;
logic reset=0;  

//default clocking ve disable iff yapılıyor, checker bunlardan clock ve reset'i çekiyor.  
default clocking @ (posedge clk); endclocking
default disable iff reset;  

//=================================================
// Drive the input vectors to test assetion
//=================================================
initial begin
  // Init all the values
  reset  <= 0;
  for (int i = 0; i < 3; i++) begin
    req[i] <= 0;
    gnt[i] <= 0;
  end
  @ (posedge clk);
  req[0] <= 1;
  @ (posedge clk);
  gnt[0] <= 1;
  req[0] <= 0;
  @ (posedge clk);
  gnt[0] <= 0;
  req[1] <= 1;
  @ (posedge clk);
  req[1] <= 0;
  repeat(3) @ (posedge clk);
  gnt[1] <= 1;
  @ (posedge clk);
  gnt[1] <= 0;
  req[2] <= 1;
  gnt[2] <= 1;
  @ (posedge clk);
  req[2] <= 0;
  gnt[2] <= 0;
  // Cause assertion to fail
  @ (posedge clk);
  req[0] <= 1;
  repeat(2) @ (posedge clk);
  gnt[0] <= 1;
  req[0] <= 0;
  #30 $finish;
end
  //initialize checker check_1
  checker_1  c1 (3, req[1] ,gnt[1]);
	
  initial begin
    $dumpfile("dump.vcd"); 
    $dumpvars;    
  end
endmodule
4

In reply to hcglu:

Sorry, this is the first i see those system tasks. Is there any reason why you are using those ?

5

In reply to Rsignori92:

Problem is not about these system taks. They work. You can pass directly clock or rest. Problem is about that I cannot pass srquence to checker but this is allowed according to LRM.

6

In reply to hcglu:
… " cannot pass srquence to checker"
That would be a tool limitation.
It’s not uncommon for a tool not to implement all the features of the language

7

In reply to ben@SystemVerilog.us:

I tried with other tools Synopsis aldec, Questa, it does not work.

Thank you Ben, I tackled many obstacles on my code with your and Dave posts.

8

In reply to hcglu:

I perfectly get your problem, my question was why you were using those tasks? (never seen before). Regards

9

In reply to Rsignori92:

Iy is a differences between putting sequences and properties into a module or checker. If you use checker you can infer clock and reset from related block’s clock and reset. You can pass explicitely. In addition you can pass sequence to a checker but I could not.

I would choose to pass explicitly for making easy debugging and avoiding from complexity.

10

In reply to hcglu:

Perfect so there is no real reason or advantage why should be using those tasks instead of passing signals explicitly.

I believe you are using those along with the checker for reusability so, not for non deterministic modelling am i right? Just trying to get more from the usage you are doing. Regards

11

In reply to Rsignori92:

Exactly, increasing reusabllity and compactness. You can check LRM for more info.

12

In reply to hcglu:

That is exactly the reason why I asked you, the SV LRM 3.1a doesn’t mention it (unless I missed it while stepping into it). Usually, the properties are encapsulated in interfaces (fore reuse and encapsulation). So probably is an old approach? Just curious

13

In reply to Rsignori92:

It is not old approach Rsignorio92, you can find it in IEEE Std 1800™-2017 which is IEEE SystemVerilog Standard, 2017.

14

In reply to hcglu:

For some reason, the LRM I was looking at did not have it. Cool I found it in section 17. Thanks