Partial array randomization

SystemVerilog
1

I can’t randomize entire array like void’(randomize(taddr) with {… }, need to preserve some bits. but getting compile error when trying to selectively randomize some bits. Is there a way to do this?

void’(randomize({taddr[27],taddr[20], taddr[15], taddr[13], taddr[11:10], taddr[7:6]}) with {
addr[6]^addr[23]^addr[26]^addr[30]^addr[36]^addr[37] == taddr[6]^taddr[23]^taddr[26]^taddr[30]^taddr[36]^taddr[37];});

Error-[IATRC] Illegal argument to randomize call
ccm_seq_pkg, “{\this .taddr[27], \this .taddr[20], \this .taddr[15], \this .taddr[13], \this .taddr[11:10], \this .taddr[7:6]}”
Arguments to randomize call are limited to the names of the properties of
the calling object. Expressions like {\this .taddr[27], \this .taddr[20],
\this .taddr[15], \this .taddr[13], \this .taddr[11:10], \this .taddr[7:6]}
are not allowed.
Remove the argument {\this .taddr[27], \this .taddr[20], \this .taddr[15],
\this .taddr[13], \this .taddr[11:10], \this .taddr[7:6]} from the
randomize() call.

2

In reply to S2011:
You’ll need to create a separate variable. You can either randomize the separate variable and just move the bits you want into taddr, or you can copy the value of taddr to that variable before calling randomize and constrain the bits you don’t want randomized.

3

yes I tried that same thing, it seems to be working. Thanks!

class my_class;
rand bit bit_32, bit_31;
rand bit bit_28, bit_27, bit_24, bit_23, bit_22, bit_20;
rand bit bit_19, bit_17, bit_15, bit_13, bit_11, bit_10;
rand bit bit_9, bit_7, bit_6;
endclass

void’(my_class_h.randomize() with {
addr[6]^addr[23]^addr[26]^addr[30]^addr[36]^addr[37] == my_class_h.bit_6^my_class_h.bit_23^taddr[26]^taddr[30]^taddr[36]^taddr[37];