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Parametrized Assertion

SystemVerilog 4884
#systemverilog 412 #systemverilog #ASSERTION 59
tejasakulu
tejasakulu
Full Access
40 posts
January 13, 2021 at 2:26 pm

Hi,

I have the following assertion :

module assertions ();
`define TOP                     top.d.desin_inst
 
 
 
 
property fun_conn_check  ;
        @(posedge clk) disable iff(!rst)
 
 
if (sel_good)
 
             case (sel[2:0])
               3'b000:
		  if ((!good))
                   `TOP.p2_5_pad  === 1'bx
		  else
                   `TOP.p2_5_pad  === 1'bz;
.....
.....
....
 
 
 
The I/O pads p2_5_pad change from one project to another, how can i make it reusable across multiple projects. 
 
Can i use switches like these  if ($value$plusargs ....)
 
Thanks,
Tejas

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ben@SystemVerilog.us
ben@SystemVerilog.us
Full Access
1906 posts
January 13, 2021 at 3:14 pm

In reply to tejasakulu:

Have you considered the "generate.. endgenerate" construct based on the value of a parameter?
Ben systemverilog.us

tejasakulu
tejasakulu
Full Access
40 posts
January 13, 2021 at 3:21 pm

In reply to ben@SystemVerilog.us:

Quote:
In reply to tejasakulu:

Have you considered the "generate.. endgenerate" construct based on the value of a parameter?
Ben systemverilog.us

How can i just change the I/O pads with generate ? p2_5_pad i need to change only this to different pads say p2_1_pad and i need to achieve this via command line args

dave_59
dave_59
Forum Moderator
8446 posts
January 13, 2021 at 10:35 pm

In reply to tejasakulu:

It would certainly help to simplify by providing a property argument

property fun_conn_check (pad) ;
        @(posedge clk) disable iff(!rst)
        if (sel_good)
             case (sel[2:0])
               3'b000:
		  if ((!good))
                   `pad  === 1'bx
		  else
                   pad  === 1'bz;
...

Then you can define a macro on the command line that you can use when you compile the code

assert property ( fun_conn_check ( `TOP . `PAD ) );

Then when you compile your code, add the switch +define+PAD=p2_1_pad, or +define+PAD=p2_5_pad as needed.

— Dave Rich, Verification Architect, Siemens EDA

ben@SystemVerilog.us
ben@SystemVerilog.us
Full Access
1906 posts
January 14, 2021 at 9:12 am

In reply to dave_59:
Thanks, I like the solution. Thus, with a new definition of a `define value at the command compilation line, one may want to use that value in the generate statement.
1800'2017 shows this example: 

generate
  if ( max_quiet == 0) begin
    property quiet_time;
      @(posedge clk) reset_n |-> ($countones(en) == 1);
    endproperty
    a1: assert property (quiet_time);
   end
   else begin
   property quiet_time;
     @(posedge clk)
     (reset_n && ($past(en) != 0) && en == 0)
         |->(en == 0)[*min_quiet:max_quiet] ##1 ($countones(en) == 1);
   endproperty
   a1: assert property (quiet_time);
   end
  if ((min_quiet == 0) && ($isunbounded(max_quiet)) $warning(warning_msg);
endgenerate

Ben SystemVerilog.us

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