module assertions ();
`define TOP top.d.desin_inst
property fun_conn_check ;
@(posedge clk) disable iff(!rst)
if (sel_good)
case (sel[2:0])
3'b000:
if ((!good))
`TOP.p2_5_pad === 1'bx
else
`TOP.p2_5_pad === 1'bz;
.....
.....
....
The I/O pads p2_5_pad change from one project to another, how can i make it reusable across multiple projects.
Can i use switches like these if ($value$plusargs ....)
Thanks,
Tejas
In reply to tejasakulu:
Have you considered the “generate… endgenerate” construct based on the value of a parameter?
Ben systemverilog.us
How can i just change the I/O pads with generate ? p2_5_pad i need to change only this to different pads say p2_1_pad and i need to achieve this via command line args
In reply to dave_59:
Thanks, I like the solution. Thus, with a new definition of a `define value at the command compilation line, one may want to use that value in the generate statement.
1800’2017 shows this example:
generate
if ( max_quiet == 0) begin
property quiet_time;
@(posedge clk) reset_n |-> ($countones(en) == 1);
endproperty
a1: assert property (quiet_time);
end
else begin
property quiet_time;
@(posedge clk)
(reset_n && ($past(en) != 0) && en == 0)
|->(en == 0)[*min_quiet:max_quiet] ##1 ($countones(en) == 1);
endproperty
a1: assert property (quiet_time);
end
if ((min_quiet == 0) && ($isunbounded(max_quiet)) $warning(warning_msg);
endgenerate