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  • parameter and generate usage in the interface

parameter and generate usage in the interface

SystemVerilog 4983
generate 9 #systemverilog 430 parameter 10
megamind
megamind
Full Access
44 posts
April 06, 2018 at 3:07 pm

I have two parameters one is ENABLE_DISABLE and another is a number NUM_OF_INTERFACES.
Now when enable_disable is 1 it should generate blocks but when enable_disable is 0 then it should not generate any of the

parameter NUM_OF_INTERFACES=5;
parameter ENABLE_DISABLE=1;

Below code works well,
generate
for (i=0; i< (NUM_OF_INTERFACES); i++) begin: GEN_BLOCK
checker_interface monitor_if();
end
endgenerate

Below codes don't work, where basically I want to generate blocks based on ENABLE_DISABLE value.
1)
generate
for (i=0; i< (NUM_OF_INTERFACES & ENABLE_DISABLE); i++) begin: GEN_BLOCK
checker_interface monitor_if();
end
endgenerate

2)
generate
if (ENABLE_DISABLE == 1) begin
for (i=0; i< (NUM_OF_INTERFACES); i++) begin: GEN_BLOCK
checker_interface monitor_if();
end
end
endgenerate

Anybody have an idea? Thank you.

Replies

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Solution

Solution

sharvil111
sharvil111
Full Access
176 posts
April 08, 2018 at 4:43 am

In reply to megamind:

We can use conditional generate statement inside generate loop. We can create the instance of monitor_if based on the value of ENABLE_DISABLE inside a for loop. The below code will iterate NUM_OF_INTERFACES times and it will check the value of ENABLE_DISABLE for each iterator value. 

module top();
 
parameter NUM_OF_INTERFACES=5;
parameter ENABLE_DISABLE=0;
 
  genvar i;
  generate
    for(i=0;i<NUM_OF_INTERFACES;i++) begin: GEN_BLOCK
      if(ENABLE_DISABLE) begin: GEN_EN_BLOCK
        checker_interface monitor_if();
      end // if
    end // for
  endgenerate
endmodule

Alternatively, we can first check the value of ENABLE_DISABLE and then start the loop. This is same as 2nd point in your code.

module top();
 
parameter NUM_OF_INTERFACES=5;
parameter ENABLE_DISABLE=0;
 
  genvar i;
  generate
    if(ENABLE_DISABLE) begin: GEN_EN_BLOCK
      for(i=0;i<NUM_OF_INTERFACES;i++) begin: GEN_BLOCK
        checker_interface monitor_if();
      end // for
    end // if EN_DIS
  endgenerate
endmodule

Refer to IEEE 1800-2012 Section 27.5 for more information.

- sharvil111 | ASIC Verification

megamind
megamind
Full Access
44 posts
April 09, 2018 at 3:43 pm

In reply to sharvil111:

Thank you for your help. It works.

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