Dear Forum,
Has anyone experience on implementing pairwaise test generation in System Verilog?
Any feedkback, info from such experience would be helpful.
Just for info:
pairwise testing in kind of good alternative for exhaustive testing.
In reply to haykp:
From DVCon 2020: http://www.verilab.com/files/parameterize_like_a_pro_web_final.pdf