PACKED PARAMETER OVERRIDE

SystemVerilog
,
1

Hi,

how to override packed parameter from file operation.
file contains file.txt

'{'{50,50,50,50,},'{ 3, 3, 3, 3,},'{18,18,18,18,},'{33,33,33,33,}}
'{'{ 0, 0, 0, 0,},'{ 9, 9, 9, 9,},'{ 5, 5, 5, 5,},'{44,44,44,44,}}
'{'{56,56,56,56,},'{40,40,40,40,},'{32,32,32,32,},'{36,36,36,36,}}

module PARAM_OVERRIDE();
parameter [5:0]PARAM[4][4]='{};
endparameter

module tb();
PARAM_OVERRIDE overide();
endmodule

thank you.

2

In reply to LOHIHTHA DM:

You cannot change parameter values during simulation. You could read the file with a Perl/python script and generate proper SystemVerilog syntax:

module PARAM_OVERRIDE();
  parameter [5:0]PARAM[4][4]='{default:0};
  initial $display("%m %p",PARAM);
endmodule
module tb();
  PARAM_OVERRIDE #(.PARAM( 
    '{'{50,50,50,50},'{ 3, 3, 3, 3},'{18,18,18,18},'{33,33,33,33} }
  ) ) overide1();
  PARAM_OVERRIDE #(.PARAM( 
   '{'{ 0, 0, 0, 0},'{ 9, 9, 9, 9},'{ 5, 5, 5, 5},'{44,44,44,44}}
  ) ) overide2();
  PARAM_OVERRIDE #(.PARAM( 
   '{'{56,56,56,56},'{40,40,40,40},'{32,32,32,32},'{36,36,36,36}}
  ) ) overide3();
endmodule

# tb.overide1 '{'{50, 50, 50, 50}, '{3, 3, 3, 3}, '{18, 18, 18, 18}, '{33, 33, 33, 33}}
# tb.overide2 '{'{0, 0, 0, 0}, '{9, 9, 9, 9}, '{5, 5, 5, 5}, '{44, 44, 44, 44}}
# tb.overide3 '{'{56, 56, 56, 56}, '{40, 40, 40, 40}, '{32, 32, 32, 32}, '{36, 36, 36, 36}}