Packed dimension for integer vs. bit vector

SystemVerilog
,
1

Hi VA,

When trying to run next code on EDA Playground:


// This is the class that we will randomize.
class my_item;
  rand byte[31:0] m_array_d[];
  
  // Randomization constraints.
  constraint array_size_c {
    m_array_d.size() inside {[1:8]};
  }
  ...
endclass

I receive next error:
ERROR VCP5286 “Packed dimension cannot be specified for integer atom type.” “testbench.sv” 7 31

when changing the code to:


rand bit[7:0][31:0] m_array_d[];

No error is received, and the values in the dynamic array are randomized.
Can maybe someone point out why is that?
Any reference to this in LRM?

Thanks,
Michael

2

In reply to Michael54:

The LRM section 6.8 Variable declarations and the BNF A.2.2.1 Net and variable types do not allow it.

data_type ::=
    integer_vector_type [ signing ] { packed_dimension }
  | integer_atom_type [ signing ]

byte is an integer_atom_type. The reason behind this rule is mostly historical.

In Verilog and many programming languages, the width of atom types like integer, byte, int are left unspecified. It was this way in early versions of SystemVerilog as well. Packing an unsized integer into a struct or array does not make much sense.

Also prior to SystemVerilog some Verilog coders were using

integer [63:0] myvar;

indicating you wanted
myvar to be a 64-bit integer. However, no tool ever implemented this, they just ignored it. That created legacy code issues because you didn’t know if they were trying to specify a 64-bit integer, or 64-32-bit packed vectors.

History aside, the current SystemVerilog syntax makes it very clear how many dimensions you are working with and the bit range ordering you want.

3

In reply to dave_59:

Thank you Dave :)
We are blessed to have someone like you in the hardware verification field, sharing with us precious knowledge and history/legacy aspects.