Packed arrays of nettype real

SystemVerilog
,
1

In LRM Chapter 6.6.8, a packed array of nettype real is declared and assigned to an unpacked array without explicit casting:

package NetsPkg;
  nettype real realNet;
endpackage : NetsPkg

module driver
  import NetsPkg::*;
  #(parameter int delay = 30,
  int iterations = 256)
 (output realNet [0:1] out);

  timeunit 1ns / 1ps;

  real outR[1:0];
  assign out = outR;
  initial begin
    outR[0] = 0.0;
    outR[1] = 3.3;
    for (int i = 0; i < iterations; i++) begin
      #delay outR[0] += 0.2;
      outR[1] -= 0.2;
    end
  end
endmodule : driver

Indeed, this would be an interesting feature but I could not found any explanation why this is allowed.
Have I overlooked anything?

Thanks
Thomas

2

In reply to Thomas Kruse:

This example has an error. 0006603: Error in example of generic interconnect in 6.6.8: use of packed dimension on user-defined nettype realNet - Accellera Mantis