Packed array to unpacked array and vice versa?

SystemVerilog
1

Hi,

I have a requirement where I have two types of packed arrays from which I need to convert into unpacked array and similarly on the other side pack the data from unpacked array into a packed array.

case (a) bit [3:0] [2:0] a < - > bit [11:0] b

case (b) bit [1:0] [3:0] [2:0] a1 < - > bit [23:0] b1

I don’t quite understand how to streaming operators could be used to get this working.

Any help with an example would be greatly appreciated.

Thanks,
Madhu

2

In reply to mseyunni:

Bit-stream casting and the streaming operators work very simplistically when dealing with fixed sized arrays containing the exact same number of bits. The assignment

a = {>>{b}};

streams left-to-right. This means the MSBs on the RHS of the assignment get assigned to the MSBs on the LHS of the assignment.

a[3][2] = b[11];
a[3][1] = b[10];
a[3][0] = b[9];
a[2][2] = b[8];
...
a[0][0] = b[0];

If you had the assignment

a = {<<{b}};

streams right-to-left. This means the LSBs on the RHS of the assignment get assigned to the MSBs on the LHS of the assignment.

a[3][2] = b[11];
a[3][1] = b[0];
a[3][0] = b[1];
a[2][2] = b[2];
...
a[0][0] = b[11];

You can also stream right-to-left in blocks.

a = {<< 3 {b}};

a[3][2] = b[2];
a[3][1] = b[1];
a[3][0] = b[0];
a[2][2] = b[3];
...
a[0][0] = b[9];

If none of these operations work for your bit-ordering, you may need to use a foreach loop.

3

In reply to dave_59:

Hi Dave,
Thank you for the answers & explanation.

[quote]In reply to mseyunni:

If you had the assignment

a = {<<{b}};

streams right-to-left. This means the LSBs on the RHS of the assignment get assigned to the MSBs on the LHS of the assignment.

a[3][2] = b[11];
a[3][1] = b[0];
a[3][0] = b[1];
a[2][2] = b[2];
...
a[0][0] = b[11];


I guess you meant a[3][2] = b[0] right?


Can you explain how the other case works as it has 3 dimensions?
4

In reply to dave_59:

In terms of words, case (a) is a packed array of 4 3-bit elements. Is case (b) expressed as an array of 2 elements with each element being 4 3-bit elements. What is the layout of the bits in case(b)

5

In reply to dave_59:

for this case,

a = {<< 3 {b}};


a[3][2] = b[2];
a[3][1] = b[1];
a[3][0] = b[0];
a[2][2] = b[5];
a[2][1] = b[4];
a[2][0] = b[3];
a[1][2] = b[9];
a[1][1] = b[8];
a[1][0] = b[6];
a[0][2] = b[11];
a[0][1] = b[10];
a[0][0] = b[9];

Is this the complete assignment?

similarly could you give an example and explain b to a and b1 to a1 as well?

Thanks,

6

In reply to mseyunni:
It is explained in 11.4.14.1 Concatenation of stream_expressions.

In any case, I suggest you try some experiments on your own. Then if there’s a case whose results you cannot explain, post the example here.