Packed and Unpacked Arrays

SystemVerilog
,
1

I really need some helps:
I have an struct

typedef struct {logic single_packet[0:21]; logic header_code[3:0]; logic data_code [3:0]; } packet_s;

and I used it as follow

task Tdosomething(input packet_s packet)
logic header [3:0] = packet.header_code;
if (header == 4'b0000)
   do_something;
else
   do_something_else;
endtask: Tdosomething

I got the error message : expecting datatype compatible with 'unpacked array[3:0] but fond 'packed array [3:0] of logic instead
I have no idea where the packed array come from. Any help is appreciated very much.

2

In reply to son la:

Change your struct to

typedef struct {logic [0:21] single_packet; logic [3:0] header_code; logic [3:0] data_code ; } packet_s;
3

In reply to son la:

Thank you very much. A follow up question: should most “regular” arrays declared as unpacked array?

4

In reply to son la:

It depends what you want to model. See Difference between Packed and UnPacked Arrays | Verification Academy

5

In reply to dave_59:

Thank you again. Excellent reference