Overriding constraint

SystemVerilog
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1

Hi,I have a doubt regarding overriding constraints,this question was asked to me in an interview but I couldn’t reply.

So I know that for overriding constraint we need extend the class and provide the same constraint name as the constraint provided in the parent class but for the below case overriding is happening even if I don’t provide the same name.

constraint C1 { a>5 ;}
constraint C2 { a>10 ;}

So the constraint C2 is still overriding the C1 constraint and randomization will happen according to C2 constraint.

2

In reply to Shiv_coder:

C2 is not an override; it is an additional constraint. Both C1 and C2 constraints can be satisfied together. (Like a == 11)

An constraint override replaces an existing constraint. For example { a < 4; }. That constraint cannot be satisfied without overriding C1 or turning the constraint off.