Override the defualt disable iff(rst) for a set of properties?

SystemVerilog
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1

Is there a way to override the defualt disable iff(rst) for a particular property ?

  default disable iff (rst);

I want to cover the following case when reset is enabled… can i override the above statement only for this property ?

 COV_SV_RESET_DURING_XFER: cover property ((valid && ready) ##[0:$] rst);
2

According to the SV LRM section 16.15 page 439

The following rules apply for resolution of the disable condition:
a) If an assertion has a disable iff clause, then the disable condition specified in this clause shall be used and any default disable iff declaration ignored for this assertion.

So I believe you can implement your property with a specific disable iff which can be true or false according to your needs.

I hope this helps

-R