Output of fork join_any

SystemVerilog
,
1 
module fork_join;
  initial begin
    $display("*********************************");
    fork
      begin
        #5;
        $display($time,"\tProcess-1 Finished");
      end
      begin
        #20;
        $display($time,"\tProcess-2 Finished");
      end
       begin
        #10;
        $display($time,"\tProcess-3 Finished");
      end
    join_any
    #5;
    $display($time,"\tOutside1 Fork-Join");
    #10;
    $display($time,"\tOutside2 Fork-Join");
    $display("**********************************");
  end
endmodule

output:
                    5   Process-1 Finished
                    10	Process-3 Finished
                    10	Outside1 Fork-Join
                    20	Process-2 Finished
                    20	Outside2 Fork-Join
why not like this:
                    5   Process-1 Finished
                    10	Outside1 Fork-Join
                    10	Process-3 Finished
                    20	Outside2 Fork-Join
                    20	Process-2 Finished
2

In reply to muku_383:

Both would be legal interpretations of Verilog scheduling, so the simulator is free to pick.

3

In reply to muku_383:

Use wait fork if you expect strict order.