I’m trying basic SystemVerilog assertions. Following is dut code:
module desig (
input clk,
input [3:0] uop_i,
input flush,
output logic[3:0] uop_r
);
always_ff @ (posedge clk) begin
if (flush)
uop_r <= 'b0;
else
uop_r <= uop_i;
end
sequence c1;
((flush =='b1) ##1 (uop_r=='b0));
endsequence
property check;
@(posedge clk) c1;
endproperty
assert property (check) $strobe("AP | [%4t] | uop_i=%h | flush=%b | uop_r=%h | $past(uop_i)=%h", $time, uop_i, flush, uop_r, $past(uop_i, 1));
else $error("AF | [%4t] | uop_i=%h | flush=%b | uop_r=%h | $past(uop_i)=%h", $time, uop_i, flush, uop_r, $past(uop_i, 1));
endmodule
Following is my testbench code:
module testbench;
reg clk;
reg [3:0] uop_i;
reg flush;
wire [3:0] uop_r;
desig dut(clk, uop_i, flush, uop_r);
initial begin:CLOCK
clk = 1'b0;
forever #10 clk = ~clk;
// repeat(500) #10 clk = ~clk;
end
initial begin
for (int i=0;i<10;i++) begin
uop_i = $random;
flush = $random;
$strobe("AX | [%4t] | uop_i=%h | flush=%b | uop_r=%h", $time, uop_i, flush, uop_r);
@(posedge clk);
$display("");
end
#20 $stop;
end
endmodule
I’m running it on Questasim and following is my output:
AX | [ 0] | uop_i=4 | flush=1 | stall=1 | uop_r=x
AX | [ 10] | uop_i=3 | flush=1 | stall=1 | uop_r=0
AP | [ 30] | uop_i=5 | flush=0 | stall=1 | uop_r=0 | $past(uop_i)=4
AX | [ 30] | uop_i=5 | flush=0 | stall=1 | uop_r=0
**# ** Error: AF | [ 50] | uop_i=d | flush=0 | stall=1 | uop_r=5 | $past(uop_i)=3
Time: 50 ns Started: 50 ns Scope: testbench.dut File: D:/gdrive_upload/Work/RV_Verif/Salman/modelsim_practice/desig.sv Line: 41
AP | [ 50] | uop_i=d | flush=0 | stall=1 | uop_r=5 | $past(uop_i)=3
AX | [ 50] | uop_i=d | flush=0 | stall=1 | uop_r=5**
** Error: AF | [ 70] | uop_i=d | flush=0 | stall=1 | uop_r=d | $past(uop_i)=5
Time: 70 ns Started: 70 ns Scope: testbench.dut File: D:/gdrive_upload/Work/RV_Verif/Salman/modelsim_practice/desig.sv Line: 41
AX | [ 70] | uop_i=d | flush=0 | stall=1 | uop_r=d
** Error: AF | [ 90] | uop_i=6 | flush=1 | stall=0 | uop_r=d | $past(uop_i)=d
Time: 90 ns Started: 90 ns Scope: testbench.dut File: D:/gdrive_upload/Work/RV_Verif/Salman/modelsim_practice/desig.sv Line: 41
AX | [ 90] | uop_i=6 | flush=1 | stall=0 | uop_r=d
# AX | [ 110] | uop_i=5 | flush=1 | stall=0 | uop_r=0
AP | [ 130] | uop_i=f | flush=0 | stall=0 | uop_r=0 | $past(uop_i)=6
AX | [ 130] | uop_i=f | flush=0 | stall=0 | uop_r=0
** Error: AF | [ 150] | uop_i=8 | flush=1 | stall=0 | uop_r=f | $past(uop_i)=5
Time: 150 ns Started: 150 ns Scope: testbench.dut File: D:/gdrive_upload/Work/RV_Verif/Salman/modelsim_practice/desig.sv Line: 41
AP | [ 150] | uop_i=8 | flush=1 | stall=0 | uop_r=f | $past(uop_i)=5
AX | [ 150] | uop_i=8 | flush=1 | stall=0 | uop_r=f
AX | [ 170] | uop_i=d | flush=1 | stall=1 | uop_r=0
AP | [ 190] | uop_i=d | flush=1 | stall=1 | uop_r=0 | $past(uop_i)=8
** Note: $stop : D:/gdrive_upload/Work/RV_Verif/Salman/modelsim_practice/testbench.sv(27)
Time: 210 ns Iteration: 0 Instance: /testbench
For now, I’m only trying to verify assertion on the flush condition.
The Question is:
[*] Why clock 50 is displayed 3 times and then missing the assertions $strobe statement in clock 110. It should show assertion pass statement at 110 and display only assertion fail at 50.