Order of Execution in below sample example?

SystemVerilog
,
1 
module tb;
wire p;
logic q;
  
assign p = q;
always@(*) $display($time," A pq", p,"  " ,q);
    

initial begin
	q =  0;
	$display($time," i pq", p, "  " ,q);
end	
endmodule

In this example,
q=0;// is assigned in active region, now the current process can either suspend and trigger update event for assign statement and always procedure or continue executing $display (which is in the initial block), let’s say current process suspends then which one will be executed first, assign/always?

Thanks

2

In reply to DDN:

Please use code tags making your post easier to read. I have added them for you.

All of it is indeterminate. See section 4.7 Nondeterminism in the 1800-2017 LRM.