Optional task arguements

SystemVerilog
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1

Hi there!

I am using an existing verification environment that includes some tasks that drive a BFM. For example:

axi_lite_wr(input bit [31:0] addr, input bit [31:0] data);

I would like to add a verbosity level as an optional input to the task. I don’t want to break other peoples test environments, so I don’t want to force people to use a third argument, like “int verbosity” as shown below:

axi_lite_wr(input bit [31:0] addr, input bit [31:0] data, int verbosity);

I could make another task like this:

GLOBAL_VERBOSITY_LEVEL_IN_BFM = 0;
task axi_lite_wr_verbosity(input bit [31:0] addr, input bit [31:0] data, int verbosity);

GLOBAL_VERBOSITY_LEVEL_IN_BFM = verbosity;
axi_lite_wr(addr, data);
endtask

But I am wondering if there is a more elegant way to do this.

thank you!

2

In reply to aale:


axi_lite_wr(input bit [31:0] addr, input bit [31:0] data, int verbosity = default_value);