Optional output/ref arguments in a function

SystemVerilog
1

extern virtual function void read_line(<*old arg>, ref bit value=1’b0 );

Is it possible to add optional ref/output arguments for a function? I am adding a new argument now, but don’t want to change all the old files which need this same function except for 1 file where I need this new argument but uses the same function in several places.

Illegal connection to the ref port ‘value’ of function/task
‘model_pkg_c_2149966356_29::read_line’,formal argument
should have same type as actual argument.

Thanks,
Anu

2

In reply to S2011:

You can do this, but the default argument needs to compatible as if it was actually used as an argument. You cannot pass a constant literal in the place of a ref argument. You will need to write

bit dummy;
extern virtual function void read_line(<**old arg*>, inout bit value=dummy );

Now dummy is the variable used by read_line.

BTW, there are very few good reasons to ever use “ref” as a function argument direction. Much better to use input, output or inout as these have fewer restrictions than ref.

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