Not able to display `define macro argument in $display

SystemVerilog
1

Hi,

This macro is not displaying string which is passed in `define macro argument.

`define SIGP_AG_TRG_VLD_CHK(accel_sensor,gyro_sensor,axis)\
                always_comb begin\
                  if( (``accel_sensor``_assertion_en | ``gyro_sensor``_assertion_en) & sigp_ag_rst_b) begin\
            sigp_ag_ui_trg_``axis``_chk :assert final (((``accel_sensor``_ui_trg_``axis`` | ``gyro_sensor``_ui_trg_``axis`` ) & ((``accel_sensor``_ui_vld_``axis`` | ``gyro_sensor``_ui_vld_``axis``))===1)  || ((!``accel_sensor``_ui_trg_``axis`` & !``gyro_sensor``_ui_trg_``axis``)===1) ) \
                            $display(" %0t : [ag_assertion_if] sigp_ag_ui_trg_%s PASS",$time,``axis`` ); \               // this is not displaying %s
                  else\
                            $error(" %0t : [ag_assertion_if] sigp_ag_ui_trg_%0s FAIL",$time,``axis`` ); \                // this is not displaying %s
                  end\
                end

Tool Behavior__
3504282000 : [ag_assertion_if] sigp_ag_ui_trg_ PASS
3609673000 : [ag_assertion_if] sigp_ag_ui_trg_ PASS
3610641000 : [ag_assertion_if] sigp_ag_ui_trg_ PASS
3612577000 : [ag_assertion_if] sigp_ag_ui_trg_ PASS

2

In reply to Divyesh Nariya:

You should write your $display with
`“axis`” instead of
``axis``