module tb;
reg clk;
initial clk=1'b0;
always
begin
clk<= #70 0;
clk<= #30 1;
end
initial
begin
#800;
$finish;
end
initial
begin
$dumpvars(1);
$dumpfile("dump.vcd");
end
endmodule
Hi,
On executing the above code the simulator gives the output as follows :
./run.sh: line 15: 7 Killed
I had some conclusions in my mind after checking this in the simulator but I ain’t sure if that’s the reason. Can someone tell me why does it behave like this on using a non-blocking assignment with transport delay?
Thanking You