Non-blocking assignment

i am running the below code the output is a = x and b = 0.

module code();
  wire a;
  reg b;
  assign a = 1;
  assign a = 0;
  initial
	begin
  	$monitor("a = %b,b = %b",a,b);
  	b<=1;
  	b<=0;
	end
endmodule

assign statements are implicitly parallel. that’s why a = 0.
in non-blocking assignment’s i am getting “b = 0”,why “b” value is 0;
because of both non-blocking statements are also executed in parallel.

In reply to anvesh dangeti:
Please use code tags making your code easier to read. I have added them for you.

Statements within a
begin/end
get executed in sequence, not parallel. Section 4.6 Determinism in the IEEE 1800-2017 SystemVerilog LRM has your example except your variable
b
is named
a
. The final value of
b
is 0.