No. of coverpoint autobins

SystemVerilog
1

Let’s say I have two inputs which I am sampling and have a coverpoint defined as below -


logic [2:0] a;
logic [2:0] b;

covergroup cg_exp;

  // Coverpoint1
  sum_a_b_auto : coverpoint (a + b);

  // Coverpoint2
  sum_a_b_range : coverpoint (a + b) {
   less_than_7 = {[0:6]};
   equal_to_7 = {7};
   greater_than_7 = {[8:$]};
  }

endgroup
  1. How many autobins are created for Coverpoint1
  2. Is it possible to hit the ‘greater_than_7’ bin in simulation?
2

In reply to tpan:

  1. There are 7 possible values from the result of a+b, so 7 bins are automatically created.
  2. [8:$] is the same as [8:7], which overlaps the equal_to_7 bin
3

In reply to dave_59:

Thanks, Dave

4

In reply to dave_59:
worst case scenario if a is 7 and b is 7 . cover-point output should it be 14 or cover-point will reduce the resultant bits based on its operand’s number of bits?

5

In reply to kddholak:

As a self-determined expression, 3’b7 + 3’b7 = 3’b6

6

In reply to dave_59:

Hi Dave ,

Have 2 questions ::

(1) Typically range is [low:high] , so I were to write [high:low] **would the bounds be changed from low to high internally ? .
**
(2) If I were to write ::


       // Coverpoint2
  sum_a_b_range : coverpoint (a + b + 4'b0 ) // 4-bit precision
  {
   less_than_7 = {[0:6]};
   equal_to_7 = {7};
   greater_than_7 = {[8:$]}; // Doubt here !!
  }

Will bin greater_than_7 cover range [8:14] ( i.e 7 + 7 ) OR [8:15] ( due to 4-bit precision ) ?

7

In reply to hisingh:

It is an error if you write the range [high:low]. This helps catch errors in any calculations you might have.

The LEM does not specify how the max value is specified, but I think assume (and it’s easy to verify) it is based on the type of the expression (4-bit precsion), not the maximum value the expression could yield.