New Subtypes with ranges in SystemVerilog

SystemVerilog
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1

Hello everyone,

does anyone have an idea if we can create user-defined types… which are included in a specific range, in SystemVerilog,

Something like the vhdl’s :


Subtype MySubtype is natural range 15 downto 0;

Thanks in advance.

2

In reply to Yasmine4:

SystemVerilog does not have this feature. As I mentioned to you in an earlier post, SystemVerilog has weak type system when it comes to integral types.

For your particular example you could the following to get the same effect:

typedef bit [3:0] MySubType;

For the general case, you could place assertions on variables of a particular type.