Dear SVA experts,
I have a scenario for which I am trying to write an assertion.
Please share some suggestions.
I have 4 signals - Valid, Start, End and Data.
When Valid is high, Data must remain constant between Start and End. Valid can toggle in between and when it is low, I must ignore Data.
Start and End will be high for one cycle only.
Please help how I can ignore (Valid == 0) and still keep the below thread active till End is asserted.
(Valid & Start, temp_data = Data) |=> (Data == temp_data) throughout (End[->1]); // Will work only when valid is high throughout Start to End sequence