NEED OF MONITOR

hi,

I am new to system verilog .In system verilog environment. why we require output monitor we can directly connect the dut outputs to scoreboard and the input monitor receive the inputs and gives to score board for golden model instead we can directly connect to score board. because if we connect monitor it delays the process. can i know why it is required

If I understand your question correctly, you’re asking why the need of the monitor, which collects the information and sends it to the scoreboard, since once can do the same collection within the scoreboard? The simple answer is organization, or separation of functions to individual units.

For designs that are control or protocol intensive, one need not use a monitor or scoreboard altogether if assertions are used. See my White paper: “Using SVA for scoreboarding and TB designs” http://systemverilog.us/papers/sva4scoreboarding.pdf
and a related issue at the Verification Academy the following paper
“Assertions Instead of FSMs/logic for Scoreboarding and Verification”
avaible in the verification-horizons October-2013-volume-9-issue-3
October 2013 | Volume 9, Issue 3 | Verification Academy
and SVA in a UVM Class-based Environment
SVA in a UVM Class-based Environment | Verification Horizons | Verification Academy


Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us

  • SystemVerilog Assertions Handbook 3rd Edition, 2013 ISBN 878-0-9705394-3-6
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