Need help in writing constraints

SystemVerilog
,
1

Generate constraint randomized array which has size of 10. Out of 10, Any 4 number should be odd and other 6 should be even.

2

In reply to anvesh dangeti:

This seems to be a popular interview/homework question. This might help
https://verificationacademy.com/forums/systemverilog/constraint-generate-array-random-numbers-where-certain-value-repeated-fixed-number-times#reply-51565

3

In reply to anvesh dangeti:

Hi,

Please find the below snippet with required constraints.


module test();

	class AB;
      rand bit [7:0] da[];
		
		constraint da_size{da.size == 10;}
      constraint da_val{(da.sum with (int'(item%2 == 1))) == 4;}
	endclass
	
	AB a_h = new();
	
	initial
		begin
			if(!a_h.randomize())
				$display("randomize failed");
			else
				$display("values in da are %p", a_h.da);
		end
endmodule

Hope this helps.
Putta Satish