Need to get unique random values

SystemVerilog
1

I am trying to randomize the address and create array indexes out of it. The randomized value is getting repeated here. Can I use randc while declaring the variable so that every time I get a unique randomized value?

module std_randomize;
  bit [07:0] addr;
  bit [12:0] data[bit [12:0]];

  

  initial begin
    for(int i=0; i<=200; i++)
      begin
    std::randomize(addr);
        data[addr] = addr;
    
   
      end
    $display("Value of array is %0p \n",data);
      
  end
endmodule
2

In reply to Arun_Rajha:
You can only use randc on a class variable. You should create a class just for generating addresses. Otherwise you’ll have to create a queue of previously randomize addresses

module std_randomize;
  bit [07:0] addr, used[$];
  bit [12:0] data[bit [12:0]];
 
  initial begin
    for(int i=0; i<=200; i++)
      begin
        std::randomize(addr) with {unique {addr, used};};
        used.push_back(addr);
        data[addr] = addr;
      end
    $display("Value of array is %0p \n",data);
  end
endmodule