Multiple replication operators within one dimension of an unpacked array

SystemVerilog
1

static logic [DATA_WIDTH-1:0] test_vecs[5][dot_size*2] =
‘{
{’{dot_size{MAX_NEG_INPUT}}, ‘{dot_size{MAX_POS_INPUT}}},
{’{dot_size{MAX_NEG_INPUT}}, ‘{dot_size{MAX_POS_INPUT}}},
{’{dot_size{MAX_POS_INPUT}}, ‘{dot_size{MAX_POS_INPUT}}},
{’{dot_size{MAX_POS_INPUT}}, ‘{dot_size{MAX_NEG_INPUT}}},
{’{dot_size{0}}, '{dot_size{0}}}}
};

I have been getting the following error for the above piece of code:

Number of elements in target expression does not match the number of
elements in source expression.
target Expression:
dotN_int_test_sequence.run.test_corner_inputs_outputs.unnamed$$_5.test_vecs
source Expression: ‘{’{{'{dot_size {MAX_NEG_INPUT}}, '{dot_size
{MAX_POS_INPUT}}}}, ‘{{’{dot_size {MAX_NEG_INPUT}}, '{dot_size
{MAX_POS_INPUT}}}}, ‘{{’{dot_size …

What do I do to fix this?

2

In reply to sdsawant:
Unfortunately, you can’t split an array replication operator into multiple segments within one dimension. You might change the structure of your array to make it easer to assign

  typedef logic [8-1:0] dot_t;
   typedef dot_t dot_row_t[dot_size][2];

   dot_row_t test_vecs[5]  ={
			    dot_row_t'( '{dot_size{{ MAX_NEG_INPUT, MAX_POS_INPUT}}} ),
			    dot_row_t'( '{dot_size{{ MAX_NEG_INPUT, MAX_POS_INPUT}}} ),
			    dot_row_t'( '{dot_size{{ MAX_POS_INPUT, MAX_POS_INPUT}}} ),
			    dot_row_t'( '{dot_size{{ MAX_POS_INPUT, MAX_NEG_INPUT}}} ),
			    dot_row_t'( '{default:0})
			    };