Multiple Operators in Constraint

SystemVerilog
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1

Although I won’t ever use the following constraint in an actual project , I am still trying it to understand how constraints work .

Simply specifying the following constraint ::



 constraint MB { 0 < -3 ; }

This gives randomization failure since the value returned is 0 , hence constraint failure !!

I then replace it with the following constraint ::



 constraint MB { 1 < -2 < -3 ; }

This doesn’t give randomization failure !!

Since the operators would be evaluated from Left to Right ( ( 1 < -2 ) is solved first ) so essentially isn’t the constraint same as ::



 constraint MB { 0  < -3 ; }

Any suggestions ?

2

In reply to TC_2017:

Your problem has absolutely nothing to do with SystemVerilog constraints and everything to do with how Verilog expressions work. You are correct that ( 1 < -2 ) get evaluated first, but its result is 1’b0(false), not 0. 1’b0 is unsigned, and 0 is a 32-bit signed decimal number. The result of (1’b0 < -3) is 1’b1(true) because you are mixing unsigned and signed in a relational operator, so everything becomes unsigned. (32’h00000000 < 32’hFFFFFFFD) is true.

Please see the seminar I just gave Verilog Basics for SystemVerilog Constrained Random Verification