Multiple NBA in initial block

SystemVerilog
, ,
1

In case of the following code, the last assignment wins i.e. v will be 1:


module test;
  logic v;
  initial
    begin
      v <= 0;
      v <= 1;
    end
endmodule

However, what will be the value of v if:


module test;
  logic v;
  initial
    begin
      v <= 0; //St1
      #1;
      v <= 1; //St2
    end
endmodule

Is St1 and St2 RHS evaluated in same time slot but assignment done in separate slots? I see v going from

0 -> 1

at 1ns.

2

In reply to prashantg:

Last assignment wins.

St1 executes at time 0 and updates at the before the end of time 0. Then St2 executes at time 1 and updates before the end of time 1.

3

In reply to dave_59:

Dave, in case NBAs are replaced with BAs. Both the updates will be done in Active regions of respective slots. Right?

Also, any case where logic will be X due to multiple values in the same slot?

4

In reply to prashantg:

Correct about the blocking assignment. More precisely, the updates happen before proceeding to the next statement in the initial process. The process is blocked before the update happens.

Procedural assignments to variables can only happen one at time regardless of being blocking or non-blocking. Last write wins. Only nets can give you X’s if there are multiple drivers