Multiple inheritence in SV

SystemVerilog
, ,
1

I would like to know the reasoning behind not allowing multiple inheritance in SV.
Sometimes, things look so un-intuitive just because multiple inheritance is not allowed.

For example, in the UVM class hierarchy, uvm_component is derived from uvm_report_object.
If multiple inheritance was allowed, it would actually inherit from uvm_object and from uvm_report_object.
When someone looks at uvm_component’s parent, uvm_report_object looks so in-intuitive as to why a static object in uvm has to have report object as its parent.

Any thoughts or comments?

1 Like
2

In reply to verif_learner:

I wrote a DVCon 2010 paper about it: A solution to the lack of multiple inheritance in SystemVerilog

SystemVerilog 2012 addressed the problem by adding interface classes. See this article about it.

3

In reply to dave_59:

Sure. I will take a look.