How can we perform the concept of multiple inheritance in system verilog. ie the child class is extended by two or more parent classes.
its really not supported in systemverilog for non-interface or non-abstract classes, however you can extend an interface class from multiple interface classes or create a non-interface class which implements multiple interface classes.
from SV_LRM:
The mechanism provided by SystemVerilog is called single inheritance, that is, each class is derived from a single base class.
also look into this section : 8.26 Interface classes