Multiple drivers issue in System Verilog

SystemVerilog
1

Hi,

I am Performing a write to memory location 0x00 but the write goes to 0x02. And when I read the data from 0x00 it is read out from 0x02. How can I catch such bug with system verilog constructs.

Thanks,
Shailendra

2

In reply to rajput7767:

Hi,
I am Performing a write to memory location 0x00 but the write goes to 0x02. And when I read the data from 0x00 it is read out from 0x02. How can I catch such bug with system verilog constructs.

Your question needs further clarifications on your part:

  1. Title suggests that the problem is with multiple drivers (not clear as to why)in that the requested address of 0 is somehow modified to 2 for both, writes and reads.
  2. What do you think is the issue?
  3. Do you have access to the sent address, prior to the tri-state divers? If so, you can use an assertion to verify that the address at the tri-state lines is the same as the one initiated at its source. That would be for a write assertion and a read assertion

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us

  • SystemVerilog Assertions Handbook 4th Edition, 2016 ISBN 978-1518681448
  • A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5
  • Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004, ISBN 0-9705394-6-0
  • Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 0-9705394-2-8
  • Component Design by Example ", 2001 ISBN 0-9705394-0-1
  • VHDL Coding Styles and Methodologies, 2nd Edition, 1999 ISBN 0-7923-8474-1
  • VHDL Answers to Frequently Asked Questions, 2nd Edition ISBN 0-7923-8115
3

In reply to rajput7767:

If your driver is working perfectly then you could catch this bug by backdoor access to the memory:

  1. write into the location 0x0 then the memory will be updated to location 0x2 then perform the backdoor read to all the locations in the memory then you could catch the bug.