Multiple clock in interface module

I have array of 32 bit data.it is the spi address .i have to send this data serially to DUT.the protocol to send the data is
whenever syn pulse is high( i.e at every 32ms),i should transmit the serial data(1 bit) with respect to negedge of the spi clk.
1.A 6Khz clock is generated contentious.this is spi clock.
2.For every 32ms a pulse of 100us is generated.this is sync pulse

how to use syn pulse and spi clk in clocking block of interface,so the that my serial line should be first sensitive to syn pulse after that it should be sensitive to negedge of spi
how to implement this using interface?.Is there any better idea to do this?

kindly help