Multiple assignment error

SystemVerilog
,
1

Hi,

I’m trying to compile this code:

test
#(
  parameter PARALLEL_TAPS = 2
)
(
  input  clk,
  input state,
  output reg  [31:0] out_data
);

genvar i;

generate
  for (i = 0; i < PARALLEL_TAPS ; i++)  
    begin: data_loop 
      always @(posedge clk)
        if (state)
          begin
            out_data[8*i +: 8] <= 8'h0;
          end
        else
          out_data[16*i +: 16] <= 16'h0; //data_in[i];
    end
endgenerate

For some reason, I receive this error:
Error (10028): Can’t resolve multiple constant drivers for net “out_data[15]” at syntax_test.sv(18)

The same error repeats for bit 15 to 8.

I have only 2 assignment for this net and they both are with if/else so I shouldn’t have any error of this type.

Any suggestions?

2

In reply to yonico12344:

If you expand your code manually, you will see the conflict:


test
#(
  parameter PARALLEL_TAPS = 2
)
(
  input  clk,
  input state,
  output reg  [31:0] out_data
);
 
genvar i;
 
    begin: data_loop0 
      always @(posedge clk)
        if (state)
          begin
            out_data[8*0 +: 8] <= 8'h0;  // out_data[0:7]
          end
        else
          out_data[16*0 +: 16] <= 16'h0; //out_data[0:15]  <- Conflict
    end

    begin: data_loop1
      always @(posedge clk)
        if (state)
          begin
            out_data[8*1 +: 8] <= 8'h0; // out_data[8:15]  <- Conflict
          end
        else
          out_data[16*1 +: 16] <= 16'h0; //out_data[16:31]
    end