Module method call through loop

SystemVerilog
,
1

Hi,

I know for calling any module/interface through function-for loop needs constant value. Other wise it will generate cross module error.

Example code:


module LANE();
  function reset_lane(int a);
    $display("LANE[%0d] is Reset",a);
  endfunction : reset_lane
endmodule : LANE

module top();
  LANE ln[0:15]();
  main main_i();
endmodule : top

program main();
  function start();
    for(int i=0; i<16; i++) begin
      $root.top.ln[i].reset_lane(i);
    end
  endfunction : start
endprogram : main

Now I need to target reset_lane method for each module using for loop in program-function not in program-initial.

How can I play with this scenario?

–
Regards

2

In reply to electron:

Hello,

I believe here reset_lane function in Modeule LANE is to reset perticular Lane!

If you want controlabilty from testcase, You can use abstract class method to do so. Where you dosnt have to use $root and wont be any issue to use reset_lane method to call in any Program-function.

Please refer Section 8.21 from SV LRM.

Regards,
Vinay Jain

3

In reply to Vinay Jain:

Hi Vinay,

That was just an example to define my scenario. I need to call any of the module method here reset_lane through function-loop from program block.

You can use abstract class method to do so

I don’t get this, Could you please elaborate?

4

I now use interface classes instead of an abstract/virtual classes when the abstract class only contains pure virtual methods. The benefit of using an interface class is that you can implement multiple interface classes in a single class while also extending from another class.

package my_api;
interface class lane_api;
   pure virtual function void reset_lane(int a);
endclass
endpackage

module LANE();
  function void reset_lane(int a);
     $display("LANE[%0d] is Reset",a);
  endfunction : reset_lane
   // implementation of lane_api
  class lane_api_imp implements my_api::lane_api;
     virtual function void reset_lane(int a);
	LANE.reset_lane(a);
     endfunction 
  endclass : lane_api_imp
  function lane_api_imp create;
     create = new();
  endfunction    
endmodule : LANE
 
module top();
  LANE ln[0:15]();
  main main_i();
endmodule : top
 
module main();
   import my_api::lane_api;
   
   lane_api lane_h[16];
   function automatic bit init_lane(int n, lane_api h);
      lane_h[n] = h;
   endfunction
      
for(genvar i=0;i<16;i++) begin
   // I used a static variable initialization instead of
   // an initial block to avoid race conditions with the initial
   // block below
   bit a = init_lane(i,$root.top.ln[i].create());
end
   
  function start();
    for(int i=0; i<16; i++) begin
      lane_h[i].reset_lane(i);
    end
  endfunction : start
   initial 
     start;

endmodule : main