Module Instantiation

SystemVerilog
1

Hi,

Let’s assume that I want to instantiate a module:

orig_module my_module(
.clk(clk),
.rst(rst),
.signal1(sig1)
);

My question is:
What is professional name of one the row ? For example: .signal1(sig1)
How to say ? signal1 instantiate from sig1 ?

2

In reply to alexd555:
Maybe you mean to say “port connection”. The port signal1 is connected to the signal sig1.