Module definition of instance not found in the design

SystemVerilog
, ,
1

Sorry for the elementary nature of my question since I am a new systemverilog user.

Reading the Spear book, I came across an example. I am using EDA playground to compile the code. Either of the compilers selected gives me the same result. The example is:

module logic_data_type(input logic rst_h);
  parameter CYCLE = 20;
  logic q, q_l, d, clk, rst_l;
  initial begin
    clk = 0;
    forever # (CYCLE/2) clk = ~clk;
  end
  assign rst_l = ~rst_h;
  not n1 (q_l, q);
  my_dff dl(q, d, clk, rst_l);
endmodule

The error that I get is:

"my_dff dl(q, d, clk, rst_l);"
  Module definition of above instance is not found in the design.

Clearly, if I comment out the line in question the code compiles.

What is my issue:

Thank You
Tom

2

In reply to miner_tom:

the problem is that d1 is an instance of mv_dff as the error says the definition of that module is not found in the file you compiled, it would be useful to share the EDA playground link.
You need the definition of the module somewhere:

module my_dff (input q...);
...
endmodule

HTH,
-R

3

In reply to rgarcia07:

Thank You,

I will post the EDA Playground link this evening after work.

Tom

4

In reply to rgarcia07:

Please let me know if this comes through

Tom

5

In reply to miner_tom:

It would be some thing like this see the definition of dff.

6

In reply to rag123:

In reply to miner_tom:
It would be some thing like this see the definition of dff.
(1) - EDA Playground

Thank You,

I will examine this.

Tom