Module automatic

SystemVerilog
1

Hi,

I’m just at the beginning with SV and I don’t know what means that a module is automatic. Can you help me?

Ex: module automatic name_module;

2

In reply to dariof:

See my comment about automatic program blocks. The same concepts about variable lifetimes apply to automatic modules.

Also see what is the exact difference between static tasks/functions and automatic tasks/functions ? please explain with a clear example | Verification Academy

3

In reply to dave_59:

Thanks Dave.