How to decide the direction of ports given in interface and in modports? they are so confusing. Please help me out
In reply to Muthamizh:
How to decide the direction of ports given in interface and in modports? they are so confusing. Please help me out
A SystemVerilog interface is a bundle between the DUT and the testbench.
A modport (1800’2017 25.5 Modports) restricts illegal access, like driving a signal by a driver where the modport declares that signal as an input to the driver (it should be an output of the driver).
Consider for example a loadable DUT counter where data_in is the load data. That load data signal is driven by a driver, and this is an output in the modport. See the discussion at the link below as it addresses clocking block and modports. It also provides examples.
Clocking block in interface - SystemVerilog - Verification Academy
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
For training, consulting, services: contact Home - My cvcblr
- SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
- Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 978-1539769712
- A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5
- Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004, ISBN 0-9705394-6-0
- Component Design by Example ", 2001 ISBN 0-9705394-0-1
- VHDL Coding Styles and Methodologies, 2nd Edition, 1999 ISBN 0-7923-8474-1
- VHDL Answers to Frequently Asked Questions, 2nd Edition ISBN 0-7923-8115
See Paper: VF Horizons:PAPER: SVA Alternative for Complex Assertions - SystemVerilog - Verification Academy
In reply to ben@SystemVerilog.us:
I am still not able to understand properly. Could you please explain more clearly with another simple example?