In sv the interface has modport with inout declaration which throws an error as “Illegal inout port connection to variable type” in questa simulator but there is no fault with the code written as it gets simulated with synopsys simulator. so, can you help me out with this to work in questasim.
In reply to niha1321:
We don’t discuss tools in this forum.
Edit this post and show some minimal code.
Ben systemverilog.us
In reply to ben@SystemVerilog.us:
Also, take a look at the replies at
https://verificationacademy.com/forums/systemverilog/driving-wire-task-interface.#reply-80444
Ben SystemVerilog.us