Mixing signed and unsigned numbers in sv/v

SystemVerilog
, ,
1

Hello

In below code
check1 comes out FFFF_FFF5
check2 comes out 3FFF_FFF5
check3 comes out b
I understand that when I do -44/4, -44 is expressed in 2s complement form and we divide by 4 to get answer -11 which is expressed in 2s complement form.
However in check2, my understanding is anything in base format is considered unsigned. So 6’o54 would be positive 44 in 2s complement. this would be divided by 5 to get 11. with negative sign in front, it would again take 2s complement (its like 0 - 11), so answer should be same as check1 but its different.

Thanks
Aashish

integer check1, check2, check3;
initial
begin
 check1 = -44/4
 check2 = -6'o54/4;
 check3 = 6'o54/4;
end
2

In reply to aashishs2603:

Not only is a number with a base format 6’o54 considered unsigned, but mixing signed an unsigned types in an expression becomes unsigned. Also, unary minus ‘-’ has higher precedence than division ‘/’, and the width of operands get extended before applying any operators in context. So the 32-bit unsigned value 32’o54 is negated to be become unsigned 32’h ffffffd4. That divided by 4 is 32’h 3FFFFFF5.