Mixing of ansi & non-ansi style port declaration is not legal

SystemVerilog
1

Hi,
I am getting error in NCSIM.

Errors;

*ncvlog: E,ILLPDL (./…//altera_emif_mem_model_core_ddr4_161/sim/altera_emif_ddrx_model_per_device.sv,144|13): Mixing of ansi & non-ansi style port declaration is not legal. asssign rcdif.CK_L= mem_ck_n;
|
In this CK_L is Logic type and mem_ck_n is also logic type.

why simulator is giving this type of error??/

Is any one pls help me ???/

Thanks

2

In reply to Muthuvenkatesh:

Show us your port declaration. Also is this

asssign rcdif.CK_L= mem_ck_n;

actually in your code? You have a syntax error; too many s’s in assign.

3

In reply to sbellock:

Thank u for your reply . I did very silly mistake in assign i used 3 s .Now i solved…

I need one more information about one elaboration error

ERROR:
n**celab: *E,CUVPOM: Port name ‘{Name Protected}’ is invalid or has multiple connections.
ncelab: *E,CUVPOM: Port name ‘{Name Protected}’ is invalid or has multiple connections.
ncelab: *E,CUVPOM: Port name ‘{Name Protected}’ is invalid or has multiple connections.
ncelab: E,CUVPOM: Port name ‘{Name Protected}’ is invalid or has multiple connections.
ncelab: E,CUVPOM: Port name ‘{Name Protected}’ is invalid or has multiple connections.

I am using one protected file in my environment.
what are the possible mistakes will be there for this elaboration error.In compilation no
error…

Thanks
Muthuvenkatesh