Using System verilog I have to create a test bench for a MIPS processor. In order to do this I need to create an I-cache and D-cache .dat file and I need to create a machine for an add instruction to test the pipe can anyone help me with this.
Using System verilog I have to create a test bench for a MIPS processor. In order to do this I need to create an I-cache and D-cache .dat file and I need to create a machine for an add instruction to test the pipe can anyone help me with this.