Memory read after a cycle delay

SystemVerilog
1

For the following memory model, my write happens on same cycle, but my read happens a cycle later. Any reason why?
DUT:

module memory_dut (memory_if mif);
  
  logic [31:0] m_data [7:0];
  
  always @(posedge mif.clk) begin
    if(mif.en) begin
      if(mif.wr) begin
        m_data[mif.addr] = mif.data;
     end
      else if (!mif.wr) begin
        mif.data = m_data[mif.addr];
      end
    end
  end
 
endmodule

TB:

  initial begin
     @(posedge tb_if.clk)
     tb_if.en <= 1;
     tb_if.wr <= 1;
     tb_if.addr <= 1;
     tb_if.data <= 23456;
 
    @(posedge tb_if.clk)
     tb_if.en <= 1;
     tb_if.wr <= 1;
     tb_if.addr <= 7;
     tb_if.data <= 78900;

     @(posedge tb_if.clk)
     tb_if.en <= 1;
     tb_if.wr <= 0;
     tb_if.addr <= 1;
end
2

In reply to NG:
Your assignment to mid.data should be using a non-blocking assignment. Then it is guaranteed to be available in the next clock cycle. What you have written is a race condition.