Memory Management in systemverilog

SystemVerilog
1

On Page 205 IEEE 1800-2017 session 8.29 :

The system shall automatically reclaim any object that is no longer being used. In the preceding example, all that users
do is assign null to all the variables referencing handle when they no longer need it. An object shall obj not be reclaimed while there are outstanding references to that object in any active scope, or pending nonblocking assignments to non-static members of that object.

Let us say if i have a monitor as below :


    class monitor;
      ....
      mySeqItem seq_item;
      forever begin 
        @clk;
         seq_item = mySeqItem::type_id::create("seq_item", this);          --> line 5              
        `update_sequence_item();
         analysis_port.write(seq_item);
         seq_item = null;                                                 --> line 10
      end

The seq_item is passed to scoreboard and saved in FIFO.

Question:
Will line 10 above destruct the memory created at line 5 at every @clk? If so, does it mean at every clk the memory seq_item pointing to at FIFO also got destructed?

Thanks

2

In reply to VE:

No. Line 10 just removes one of the outstanding references to a mySeqItem. When no class variable holds a handle to a mySeqItem object (and a FIFO is a queue of class variables), the object may be reclaimed.

Line 10 is unnecessary because line 5 also removes a reference to a mySeqItem object and replaces it with a different reference.